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Codes:
123-2145-4546
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738-6853-9767
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X-force 2016 (2.1.1.007)
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References

Category:3D graphics software1. Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to the layout of bit lines in a dynamic random access memory (hereinafter referred to as DRAM).
2. Description of the Prior Art
FIG. 7 of the accompanying drawings schematically shows a DRAM of the folded bit line type. The DRAM includes a memory cell array 102 having an array of memory cells arranged in the form of an array of rows and columns and a peripheral circuit 103. The memory cell array 102 is divided into a plurality of memory blocks B1 to Bm. Each memory block B is provided with a block decoder 104 for selecting its corresponding block in response to an address signal. The peripheral circuit 103 includes a circuit for selecting word lines, sense amplifiers, and data lines in accordance with the address signals.
The memory cells of the memory cell array 102 are provided with one-half of the number of
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